The logic gates such as an inverter, NAND, NOR gates are designed using MOS Current Mode Logic (MCML) is presented. The MCML families are proposed which biases the sleep transistor. MCML is found to be more efficient than the standard CMOS. For power gating the circuit uses pass gate transistors. To reduce the static power dissipation in the logic gates a distributed arrangement of sleep transistors is also proposed, designed and analyzed. The logic gates in MCML and CMOS are implemented using standard 180 NM CMOS technology. In MCML logic the power dissipation is reduced for NAND, INVERTER,NOR gates and the values are found to be 0.62, 1.96, 0.12μw respectively.