Design of Low Power Two Stage LNA using CMOS Technology

Viji K and Pandiarajan C

Abstract:

The objective of this paper is to implement the Low Noise Amplifier with high gain, low noise figure, good I/O matching and good efficiency. It uses two topologies to design a circuit with increasing the battery life time. The stage-I using the Using inductive source degeneration method. The stage-II using common source topology. This 2.4 GHz Two Stage CMOS 180nm RF Low Noise Amplifier is optimize for low noise at low current with very low power consumption .The design of Low Noise Amplifier based on capacitive FB in conjunction with ∏-match N/W. By using CMOS technique, it can be used for both analog & digital integration. The efficiency is improved and the value is found to be 75.78%.

Keywords: CMOS, LNA, Inductive Source Degeneration and Common Source Topology, ∏-Match Network

Conference Name: International Engineering Post Graduate Research Conference

Conference Date: 12, March 2015 - 13, March 2015

Pages: 181-185

Paper ID: chapter-35